0-In Announces Structural Coverage, Industry's First Unified Verification Coverage Metric
Metric links assertions, simulation and formal verification, providing actionable feedback to speed verification of SoC designs
SAN JOSE, Calif. - May 26, 2003 - Today 0-In Design Automation, the Assertion-Based Verification Company, announced a unified coverage metric, called structural coverage, which links simulation with formal verification to provide users with actionable feedback about functional verification progress.
Coverage metrics for functional verification have traditionally been based on code coverage metrics such as line, branch and finite state machines. These metrics can highlight glaring verification holes but do not reveal whether the function of a design has been well verified. Structural coverage highlights the corner cases of designs and marks them as functional verification events that must be covered, either with simulation or with formal verification. Structural coverage provides, for the first time, an automated metric that directly links coverage with functional error conditions in SoC and ASIC designs.
Structural Coverage
The three components of structural coverage are:
1. Static structural coverage - to identify verification points in RTL
2. Simulation structural coverage - to show coverage exercised by simulation
3. Formal structural coverage - to measure verification by formal analysis
Static structural coverage reports how well each section of the RTL code is covered by assertions. In particular, it points out code that requires more assertion monitoring to ensure sufficient verification. Assertions help to illuminate the internals of the design for thorough verification. Code with insufficient assertion monitoring represents dark corners of the design where bugs may be hiding.
Static structural coverage is reported as the minimum sequential distance (MSD) from each state element of the design to assertions that monitor correct functionality. Parts of a design with high MSD scores indicate low monitoring by assertions, and are candidates for increased assertion monitoring. Design and verification engineers can use static structural coverage to ensure adequate assertion monitoring of designs.
Simulation structural coverage reports how well user testbenches exercise functional corner cases. It supplements and is more meaningful than traditional line coverage. Simulation structural coverage is also the first metric that directly links functional coverage to error checking with assertions, allowing users to understand how adequately each assertion is verified.
Formal structural coverage measures the amount of formal analysis performed from each functional corner case, measured as a proof radius from the corner case. The proof radius is simply the number of cycles of exhaustive analysis from the corner case. Exhaustive formal analysis from corner cases finds bugs missed in simulation by examining all the possible events around the corner case, not just the one event exercised by simulation. This provides an improvement of a thousand-fold or more in verification coverage compared to simulation-based techniques. Users save both time and effort when verifying multi-million gate SoC designs.
Integral Component of Assertion-Based Verification
0-In's V2.0 Assertion-Based Verification (ABV) suite provides value to designers and verification engineers throughout the entire development cycle, delivering a comprehensive assertion-based verification methodology that works from block-level through system-level verification.
Users of the 0-In ABV suite have access to structural coverage as part of the CheckerWare® verification IP library. Corner case event monitoring is built into each component of the library, enabling users to specify corner case functional events automatically as they place CheckerWare elements to monitor their designs.
In addition, the 0-In ABV suite provides an integrated assertion verification report based on structural coverage spanning all products. This report provides users with a single unified view of verification progress during both simulation and formal verification.
The CheckerWare library is simulator-, testbench-, and assertion language-independent, making the assertions checkers interoperable with leading functional verification products including simulation accelerators and hardware emulators.
Structural coverage is shipping in the current release of 0-In tools.
About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
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0-In® and CheckerWare® are registered trademarks of 0-In Design Automation, Inc.
Editorial Contacts:
0-In Design Automation
Steve White, 408-487-3649, swhite@0-in.com
Cayenne Communication
Linda Marchant, 919-683-9545, linda.marchant@cayennecom.com
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